Defined in 1 files as a prototype:
Defined in 2 files as a function:
Referenced in 81 files:
- external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h, line 128
- external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
- external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h, line 185
- external/apache2/llvm/dist/llvm/lib/CodeGen/EarlyIfConversion.cpp, line 274
- external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
- external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
- external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp
- external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/Utils.cpp
- external/apache2/llvm/dist/llvm/lib/CodeGen/LiveVariables.cpp
- external/apache2/llvm/dist/llvm/lib/CodeGen/MIRVRegNamerUtils.cpp
- external/apache2/llvm/dist/llvm/lib/CodeGen/MachineCSE.cpp, line 176
- external/apache2/llvm/dist/llvm/lib/CodeGen/MachineLoopInfo.cpp
- external/apache2/llvm/dist/llvm/lib/CodeGen/MachinePipeliner.cpp
- external/apache2/llvm/dist/llvm/lib/CodeGen/MachineSSAUpdater.cpp, line 328
- external/apache2/llvm/dist/llvm/lib/CodeGen/MachineSink.cpp
- external/apache2/llvm/dist/llvm/lib/CodeGen/MachineStableHash.cpp, line 67
- external/apache2/llvm/dist/llvm/lib/CodeGen/MachineTraceMetrics.cpp
- external/apache2/llvm/dist/llvm/lib/CodeGen/ModuloSchedule.cpp
- external/apache2/llvm/dist/llvm/lib/CodeGen/OptimizePHIs.cpp
- external/apache2/llvm/dist/llvm/lib/CodeGen/PHIElimination.cpp
- external/apache2/llvm/dist/llvm/lib/CodeGen/PeepholeOptimizer.cpp, line 426
- external/apache2/llvm/dist/llvm/lib/CodeGen/RegisterCoalescer.cpp
- external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp, line 349
- external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp, line 509
- external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
- external/apache2/llvm/dist/llvm/lib/CodeGen/TailDuplicator.cpp, line 201
- external/apache2/llvm/dist/llvm/lib/CodeGen/TargetRegisterInfo.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp, line 4586
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp, line 314
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp, line 660
- external/apache2/llvm/dist/llvm/lib/Target/ARC/ARCOptAddrMode.cpp, line 409
- external/apache2/llvm/dist/llvm/lib/Target/ARM/A15SDOptimizer.cpp
- external/apache2/llvm/dist/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
- external/apache2/llvm/dist/llvm/lib/Target/ARM/ARMISelLowering.cpp, line 2746
- external/apache2/llvm/dist/llvm/lib/Target/ARM/MLxExpansionPass.cpp
- external/apache2/llvm/dist/llvm/lib/Target/ARM/MVETPAndVPTOptimisationsPass.cpp
- external/apache2/llvm/dist/llvm/lib/Target/BPF/BPFMIPeephole.cpp
- external/apache2/llvm/dist/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
- external/apache2/llvm/dist/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp, line 1504
- external/apache2/llvm/dist/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
- external/apache2/llvm/dist/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
- external/apache2/llvm/dist/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
- external/apache2/llvm/dist/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
- external/apache2/llvm/dist/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp, line 295
- external/apache2/llvm/dist/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
- external/apache2/llvm/dist/llvm/lib/Target/Hexagon/HexagonVExtract.cpp
- external/apache2/llvm/dist/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp, line 463
- external/apache2/llvm/dist/llvm/lib/Target/M68k/M68kISelLowering.cpp, line 274
- external/apache2/llvm/dist/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
- external/apache2/llvm/dist/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp, line 280
- external/apache2/llvm/dist/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
- external/apache2/llvm/dist/llvm/lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp, line 140
- external/apache2/llvm/dist/llvm/lib/Target/PowerPC/PPCBranchCoalescing.cpp
- external/apache2/llvm/dist/llvm/lib/Target/PowerPC/PPCISelLowering.cpp, line 11172
- external/apache2/llvm/dist/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
- external/apache2/llvm/dist/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
- external/apache2/llvm/dist/llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp
- external/apache2/llvm/dist/llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
- external/apache2/llvm/dist/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
- external/apache2/llvm/dist/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
- external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp, line 189
- external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/WebAssemblyFixBrTableDefaults.cpp
- external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp, line 77
- external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp, line 847
- external/apache2/llvm/dist/llvm/lib/Target/X86/X86CallFrameOptimization.cpp, line 620
- external/apache2/llvm/dist/llvm/lib/Target/X86/X86DomainReassignment.cpp, line 555
- external/apache2/llvm/dist/llvm/lib/Target/X86/X86FlagsCopyLowering.cpp, line 397
- external/apache2/llvm/dist/llvm/lib/Target/X86/X86ISelLowering.cpp, line 4571
- external/apache2/llvm/dist/llvm/lib/Target/X86/X86InstrInfo.cpp, line 4430
- external/apache2/llvm/dist/llvm/lib/Target/X86/X86InstructionSelector.cpp
- external/apache2/llvm/dist/llvm/lib/Target/X86/X86PreTileConfig.cpp