Defined in 2 files as a function:
Referenced in 64 files:
- external/apache2/llvm/dist/llvm/include/llvm/CodeGen/MachinePipeliner.h
- external/apache2/llvm/dist/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp, line 75
- external/apache2/llvm/dist/llvm/lib/CodeGen/EarlyIfConversion.cpp
- external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
- external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/Localizer.cpp
- external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
- external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp, line 157
- external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/Utils.cpp, line 211
- external/apache2/llvm/dist/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
- external/apache2/llvm/dist/llvm/lib/CodeGen/LiveIntervalCalc.cpp, line 182
- external/apache2/llvm/dist/llvm/lib/CodeGen/LiveRangeShrink.cpp
- external/apache2/llvm/dist/llvm/lib/CodeGen/LiveVariables.cpp
- external/apache2/llvm/dist/llvm/lib/CodeGen/MIRParser/MIRParser.cpp, line 348
- external/apache2/llvm/dist/llvm/lib/CodeGen/MIRPrinter.cpp, line 582
- external/apache2/llvm/dist/llvm/lib/CodeGen/MachineBasicBlock.cpp
- external/apache2/llvm/dist/llvm/lib/CodeGen/MachineBlockPlacement.cpp, line 3106
- external/apache2/llvm/dist/llvm/lib/CodeGen/MachineCSE.cpp
- external/apache2/llvm/dist/llvm/lib/CodeGen/MachineCombiner.cpp, line 157
- external/apache2/llvm/dist/llvm/lib/CodeGen/MachineDebugify.cpp, line 110
- external/apache2/llvm/dist/llvm/lib/CodeGen/MachineInstr.cpp
- external/apache2/llvm/dist/llvm/lib/CodeGen/MachineLICM.cpp, line 1012
- external/apache2/llvm/dist/llvm/lib/CodeGen/MachineLoopUtils.cpp
- external/apache2/llvm/dist/llvm/lib/CodeGen/MachinePipeliner.cpp
- external/apache2/llvm/dist/llvm/lib/CodeGen/MachineSSAUpdater.cpp
- external/apache2/llvm/dist/llvm/lib/CodeGen/MachineSink.cpp
- external/apache2/llvm/dist/llvm/lib/CodeGen/MachineTraceMetrics.cpp
- external/apache2/llvm/dist/llvm/lib/CodeGen/MachineVerifier.cpp
- external/apache2/llvm/dist/llvm/lib/CodeGen/ModuloSchedule.cpp
- external/apache2/llvm/dist/llvm/lib/CodeGen/OptimizePHIs.cpp
- external/apache2/llvm/dist/llvm/lib/CodeGen/PHIElimination.cpp
- external/apache2/llvm/dist/llvm/lib/CodeGen/PeepholeOptimizer.cpp
- external/apache2/llvm/dist/llvm/lib/CodeGen/ProcessImplicitDefs.cpp, line 67
- external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
- external/apache2/llvm/dist/llvm/lib/CodeGen/TailDuplicator.cpp
- external/apache2/llvm/dist/llvm/lib/CodeGen/UnreachableBlockElim.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp, line 3053
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp, line 1617
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp, line 7750
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp, line 582
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp, line 639
- external/apache2/llvm/dist/llvm/lib/Target/ARC/ARCOptAddrMode.cpp, line 148
- external/apache2/llvm/dist/llvm/lib/Target/ARM/A15SDOptimizer.cpp, line 368
- external/apache2/llvm/dist/llvm/lib/Target/ARM/MLxExpansionPass.cpp, line 152
- external/apache2/llvm/dist/llvm/lib/Target/BPF/BPFMIPeephole.cpp
- external/apache2/llvm/dist/llvm/lib/Target/Hexagon/BitTracker.cpp
- external/apache2/llvm/dist/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
- external/apache2/llvm/dist/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
- external/apache2/llvm/dist/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
- external/apache2/llvm/dist/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
- external/apache2/llvm/dist/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
- external/apache2/llvm/dist/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
- external/apache2/llvm/dist/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
- external/apache2/llvm/dist/llvm/lib/Target/Hexagon/RDFDeadCode.cpp, line 64
- external/apache2/llvm/dist/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp, line 114
- external/apache2/llvm/dist/llvm/lib/Target/PowerPC/PPCBranchCoalescing.cpp
- external/apache2/llvm/dist/llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp
- external/apache2/llvm/dist/llvm/lib/Target/X86/X86FlagsCopyLowering.cpp, line 311
- external/apache2/llvm/dist/llvm/lib/Target/X86/X86PreTileConfig.cpp
- external/apache2/llvm/dist/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp