Defined in 3 files as a member:
Referenced in 59 files:
- external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/Utils.h
- external/apache2/llvm/dist/llvm/include/llvm/CodeGen/MachineRegisterInfo.h, line 723
- external/apache2/llvm/dist/llvm/include/llvm/CodeGen/RegisterClassInfo.h, line 77
- external/apache2/llvm/dist/llvm/include/llvm/CodeGen/RegisterScavenging.h
- external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/Utils.cpp
- external/apache2/llvm/dist/llvm/lib/CodeGen/LiveIntervals.cpp
- external/apache2/llvm/dist/llvm/lib/CodeGen/MachineRegisterInfo.cpp
- external/apache2/llvm/dist/llvm/lib/CodeGen/RDFRegisters.cpp
- external/apache2/llvm/dist/llvm/lib/CodeGen/RegisterClassInfo.cpp
- external/apache2/llvm/dist/llvm/lib/CodeGen/RenameIndependentSubregs.cpp
- external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
- external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
- external/apache2/llvm/dist/llvm/lib/CodeGen/TargetInstrInfo.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp, line 518
- external/apache2/llvm/dist/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp, line 7435
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SIInstrInfo.h
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp, line 1682
- external/apache2/llvm/dist/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
- external/apache2/llvm/dist/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
- external/apache2/llvm/dist/llvm/lib/Target/ARM/ARMFrameLowering.cpp
- external/apache2/llvm/dist/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
- external/apache2/llvm/dist/llvm/lib/Target/ARM/ARMISelLowering.cpp
- external/apache2/llvm/dist/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
- external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp, line 10779
- external/apache2/llvm/dist/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp, line 737
- external/apache2/llvm/dist/llvm/lib/Target/ARM/MVETPAndVPTOptimisationsPass.cpp
- external/apache2/llvm/dist/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
- external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp, line 466
- external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
- external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
- external/apache2/llvm/dist/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
- external/apache2/llvm/dist/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
- external/apache2/llvm/dist/llvm/lib/Target/PowerPC/PPCInstrInfo.h, line 658
- external/apache2/llvm/dist/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
- external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/WebAssemblyPeephole.cpp
- external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
- external/apache2/llvm/dist/llvm/lib/Target/X86/X86FrameLowering.cpp
- external/apache2/llvm/dist/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
- external/apache2/llvm/dist/llvm/lib/Target/X86/X86MCInstLower.cpp
- external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp
- external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/RegisterAliasing.cpp
- external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/RegisterAliasing.h, line 45
- external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/X86/Target.cpp, line 227
- external/apache2/llvm/dist/llvm/utils/TableGen/CodeGenDAGPatterns.cpp
- external/apache2/llvm/dist/llvm/utils/TableGen/CodeGenRegisters.cpp
- external/apache2/llvm/dist/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp