Defined in 1 files as a function:

• external/apache2/llvm/dist/llvm/include/llvm/CodeGen/MachineOperand.h, line 511 (as a function)

Referenced in 28 files:

• external/apache2/llvm/dist/llvm/lib/CodeGen/BranchFolding.cpp, line 799
• external/apache2/llvm/dist/llvm/lib/CodeGen/DetectDeadLanes.cpp
  • line 551
  • line 555
• external/apache2/llvm/dist/llvm/lib/CodeGen/InlineSpiller.cpp, line 592
• external/apache2/llvm/dist/llvm/lib/CodeGen/MachineInstr.cpp, line 2022
• external/apache2/llvm/dist/llvm/lib/CodeGen/MachineOperand.cpp, line 95
• external/apache2/llvm/dist/llvm/lib/CodeGen/PeepholeOptimizer.cpp
  • line 595
  • line 1247
• external/apache2/llvm/dist/llvm/lib/CodeGen/ProcessImplicitDefs.cpp
  • line 83
  • line 111
• external/apache2/llvm/dist/llvm/lib/CodeGen/RegisterCoalescer.cpp
  • line 1358
  • line 1423
  • line 1526
  • line 1675
  • line 1686
  • line 1707
  • line 1767
  • line 1855
  • line 3087
• external/apache2/llvm/dist/llvm/lib/CodeGen/RenameIndependentSubregs.cpp, line 357
• external/apache2/llvm/dist/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp, line 423
• external/apache2/llvm/dist/llvm/lib/CodeGen/TargetInstrInfo.cpp
  • line 237
  • line 238
• external/apache2/llvm/dist/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
  • line 1622
  • line 1698
• external/apache2/llvm/dist/llvm/lib/CodeGen/VirtRegMap.cpp
  • line 577
  • line 588
• external/apache2/llvm/dist/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp, line 4245
• external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp, line 598
• external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp, line 377
• external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp, line 431
• external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp, line 319
• external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SIISelLowering.cpp, line 4164
• external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  • line 1850
  • line 1890
  • line 2414
  • line 2469
  • line 3558
  • line 6153
• external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp, line 249
• external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp, line 291
• external/apache2/llvm/dist/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp, line 1719
• external/apache2/llvm/dist/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp, line 949
• external/apache2/llvm/dist/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
  • line 1787
  • line 1825
• external/apache2/llvm/dist/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp, line 423
• external/apache2/llvm/dist/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
  • line 257
  • line 258
  • line 268
  • line 273
• external/apache2/llvm/dist/llvm/lib/Target/X86/X86ISelLowering.cpp
  • line 34104
  • line 34107