Defined in 4 files as a macro:
Defined in 4 files as a enumerator:
Referenced in 109 files:
- external/gpl3/binutils/dist/gas/bfin-lex.c, line 1309
- external/gpl3/binutils/dist/gas/rx-parse.c, line 4115
- external/gpl3/gdb/dist/sim/testsuite/d10v-elf/t-rte.s, line 13
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_except_sys_sstep.S, line 172
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_except_user_mode.S, line 207
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_disable.S, line 271
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_disable_enable.S, line 291
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_excpt.S, line 213
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_nested.S, line 208
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_nmi.S, line 227
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_pending.S, line 270
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_pending_2.S, line 205
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_timer.S, line 332
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_timer_reload.S, line 234
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_timer_tcount.S, line 190
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_timer_tscale.S, line 252
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_mmr_interr_ctl.s, line 324
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_mmr_loop.S, line 322
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_mmr_loop_user_except.S, line 218
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_mmr_ppop_illegal_adr.S, line 200
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_mmr_ppopm_illegal_adr.S, line 201
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_mmr_timer.S, line 206
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_mode_supervisor.S, line 209
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_mode_user.S, line 228
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_mode_user_superivsor.S, line 205
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_progctrl_clisti_interr.S, line 278
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_progctrl_csync_mmr.S, line 207
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_progctrl_excpt.S, line 185
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_progctrl_raise_rt_i_n.S, line 207
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ac_raise_mv.S, line 264
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ac_raise_mv_ppop.S, line 281
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ac_regmv_pushpop.S, line 281
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_dec_raise_pushpop.S, line 263
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex1_brcc_mv_pop.S, line 299
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex1_call_mv_pop.S, line 315
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex1_j_mv_pop.S, line 297
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex1_raise_brcc_mv_pop.S, line 299
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex1_raise_call_mv_pop.S, line 315
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex1_raise_j_mv_pop.S, line 297
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex2_brcc_mp_mv_pop.S, line 299
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex2_mmr_mvpop.S, line 308
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex2_mmrj_mvpop.S, line 308
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex2_raise_mmr_mvpop.S, line 307
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex2_raise_mmrj_mvpop.S, line 307
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex3_ls_brcc_mvp.S, line 323
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex3_ls_mmr_mvp.S, line 325
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex3_ls_mmrj_mvp.S, line 326
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex3_raise_ls_mmrj_mvp.S, line 325
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_wb_cs_lsmmrj_mvp.S, line 329
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_wb_raisecs_lsmmrj_mvp.S, line 329
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_wb_rti_lsmmrj_mvp.S, line 323
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_wb_rtn_lsmmrj_mvp.S, line 323
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_wb_rtx_lsmmrj_mvp.S, line 329
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/dbg_brprd_ntkn_src_kill.S, line 140
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/dbg_brtkn_nprd_src_kill.S, line 139
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/dbg_jmp_src_kill.S, line 138
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/dbg_tr_basic.S, line 230
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/dbg_tr_simplejp.S, line 225
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/dbg_tr_tbuf0.S, line 217
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/dbg_tr_umode.S, line 249
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_brtarget_stall.S, line 174
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_cc2stat_haz.S, line 212
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_cc_kill.S, line 201
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_cof.S, line 134
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_event_quad.S, line 150
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_excpt_ssstep.S, line 203
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_kill_wbbr.S, 2 times
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_disable.S, line 134
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_kill.S, line 150
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_kill_01.S, line 150
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_kill_dcr.S, line 134
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_kill_dcr_01.S, line 134
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_lr.S, line 134
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lb_stall.S, line 150
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lc.S, line 134
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lc_stall.S, line 150
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lt_stall.S, line 150
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_nest_ppm.S, line 134
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_nest_ppm_1.S, line 134
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_nest_ppm_2.S, line 134
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_ppm.S, line 134
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_ppm_1.S, line 134
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_ppm_int.S, line 133
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_lsetup_kill.S, line 134
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_misaligned_fetch.S, line 205
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_more_ret_haz.S, line 199
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_mv2lp.S, line 134
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_oneins_zoff.S, line 150
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_popkill.S, line 176
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_rts_rti.S, line 149
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_stall_if2.S, line 171
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_usermode_protviol.S, line 221
- external/gpl3/gdb/dist/sim/testsuite/sim/h8300/stack.s, line 390
- sys/arch/amiga/amiga/locore.s, line 733
- sys/arch/atari/atari/locore.s, 3 times
- sys/arch/cesfic/cesfic/locore.s, 3 times
- sys/arch/hp300/hp300/locore.s, 2 times
- sys/arch/luna68k/luna68k/locore.s, 2 times
- sys/arch/luna68k/stand/boot/locore.S, line 689
- sys/arch/m68k/m68k/reenter_syscall.s, line 68
- sys/arch/mac68k/mac68k/locore.s, 3 times
- sys/arch/mvme68k/mvme68k/locore.s, 2 times
- sys/arch/news68k/news68k/locore.s, line 858
- sys/arch/next68k/next68k/locore.s, 3 times
- sys/arch/sh3/sh3/exception_vector.S, 2 times
- sys/arch/sun2/sun2/locore.s, line 506
- sys/arch/sun3/sun3/locore.s, line 552
- sys/arch/sun3/sun3x/locore.s, line 540
- sys/arch/x68k/x68k/locore.s, 2 times