Defined in 1 files as a typedef:
Defined in 2 files as a struct:
Defined in 1 files as a prototype:
Defined in 11 files as a member:
- external/bsd/llvm/dist/llvm/include/llvm/CodeGen/FunctionLoweringInfo.h, line 58 (as a member)
- external/bsd/llvm/dist/llvm/include/llvm/CodeGen/MachineFunction.h, line 234 (as a member)
- external/bsd/llvm/dist/llvm/include/llvm/CodeGen/SelectionDAGISel.h, line 50 (as a member)
- external/bsd/llvm/dist/llvm/include/llvm/DebugInfo/DWARF/DWARFContext.h, line 95 (as a member)
- external/bsd/llvm/dist/llvm/lib/Target/ARM/ARMISelLowering.h, line 596 (as a member)
- external/bsd/llvm/dist/llvm/lib/Target/Hexagon/HexagonSubtarget.h, line 87 (as a member)
- external/bsd/llvm/dist/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp, line 797 (as a member)
- external/bsd/llvm/dist/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp, line 94 (as a member)
- external/bsd/llvm/dist/llvm/lib/Target/NVPTX/NVPTXInstrInfo.h, line 27 (as a member)
- external/bsd/llvm/dist/llvm/lib/Target/RISCV/RISCVSubtarget.h, line 44 (as a member)
- external/bsd/llvm/dist/llvm/tools/llvm-exegesis/lib/RegisterAliasing.h, line 96 (as a member)
Referenced in 81 files:
- external/bsd/llvm/dist/llvm/include/llvm/CodeGen/MachineFunction.h
- external/bsd/llvm/dist/llvm/include/llvm/CodeGen/MachineInstr.h
- external/bsd/llvm/dist/llvm/include/llvm/CodeGen/TargetInstrInfo.h
- external/bsd/llvm/dist/llvm/include/llvm/CodeGen/TargetRegisterInfo.h, line 1189
- external/bsd/llvm/dist/llvm/include/llvm/DebugInfo/DWARF/DWARFContext.h, line 307
- external/bsd/llvm/dist/llvm/include/llvm/DebugInfo/DWARF/DWARFDebugLoc.h
- external/bsd/llvm/dist/llvm/include/llvm/DebugInfo/DWARF/DWARFExpression.h
- external/bsd/llvm/dist/llvm/lib/CodeGen/DetectDeadLanes.cpp
- external/bsd/llvm/dist/llvm/lib/CodeGen/GCRootLowering.cpp
- external/bsd/llvm/dist/llvm/lib/CodeGen/MIRParser/MIParser.cpp
- external/bsd/llvm/dist/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
- external/bsd/llvm/dist/llvm/lib/CodeGen/MIRPrinter.cpp
- external/bsd/llvm/dist/llvm/lib/CodeGen/MachineBasicBlock.cpp
- external/bsd/llvm/dist/llvm/lib/CodeGen/MachineFrameInfo.cpp
- external/bsd/llvm/dist/llvm/lib/CodeGen/MachineFunction.cpp
- external/bsd/llvm/dist/llvm/lib/CodeGen/MachineInstr.cpp
- external/bsd/llvm/dist/llvm/lib/CodeGen/MachineOperand.cpp
- external/bsd/llvm/dist/llvm/lib/CodeGen/PrologEpilogInserter.cpp
- external/bsd/llvm/dist/llvm/lib/CodeGen/RegAllocGreedy.cpp, line 253
- external/bsd/llvm/dist/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
- external/bsd/llvm/dist/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
- external/bsd/llvm/dist/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
- external/bsd/llvm/dist/llvm/lib/CodeGen/StackMaps.cpp
- external/bsd/llvm/dist/llvm/lib/CodeGen/TargetRegisterInfo.cpp
- external/bsd/llvm/dist/llvm/lib/DebugInfo/DWARF/DWARFContext.cpp, line 1581
- external/bsd/llvm/dist/llvm/lib/DebugInfo/DWARF/DWARFExpression.cpp
- external/bsd/llvm/dist/llvm/lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp
- external/bsd/llvm/dist/llvm/lib/Target/AArch64/AArch64FastISel.cpp
- external/bsd/llvm/dist/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
- external/bsd/llvm/dist/llvm/lib/Target/ARC/ARCFrameLowering.cpp
- external/bsd/llvm/dist/llvm/lib/Target/ARC/ARCISelLowering.cpp
- external/bsd/llvm/dist/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
- external/bsd/llvm/dist/llvm/lib/Target/ARM/ARMFastISel.cpp
- external/bsd/llvm/dist/llvm/lib/Target/ARM/ARMFrameLowering.cpp
- external/bsd/llvm/dist/llvm/lib/Target/ARM/ARMISelLowering.cpp
- external/bsd/llvm/dist/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
- external/bsd/llvm/dist/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
- external/bsd/llvm/dist/llvm/lib/Target/BPF/BPFISelLowering.cpp
- external/bsd/llvm/dist/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp, line 85
- external/bsd/llvm/dist/llvm/lib/Target/Hexagon/HexagonSubtarget.h, line 104
- external/bsd/llvm/dist/llvm/lib/Target/Hexagon/RDFRegisters.cpp
- external/bsd/llvm/dist/llvm/lib/Target/Hexagon/RDFRegisters.h, line 149
- external/bsd/llvm/dist/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
- external/bsd/llvm/dist/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
- external/bsd/llvm/dist/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
- external/bsd/llvm/dist/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
- external/bsd/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
- external/bsd/llvm/dist/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp
- external/bsd/llvm/dist/llvm/lib/Target/Mips/MipsISelLowering.cpp
- external/bsd/llvm/dist/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
- external/bsd/llvm/dist/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
- external/bsd/llvm/dist/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
- external/bsd/llvm/dist/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
- external/bsd/llvm/dist/llvm/lib/Target/Mips/MipsSERegisterInfo.cpp
- external/bsd/llvm/dist/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
- external/bsd/llvm/dist/llvm/lib/Target/NVPTX/NVPTXInstrInfo.h, line 32
- external/bsd/llvm/dist/llvm/lib/Target/NVPTX/NVPTXPrologEpilogPass.cpp
- external/bsd/llvm/dist/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
- external/bsd/llvm/dist/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
- external/bsd/llvm/dist/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
- external/bsd/llvm/dist/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
- external/bsd/llvm/dist/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
- external/bsd/llvm/dist/llvm/lib/Target/RISCV/RISCVSubtarget.cpp, line 48
- external/bsd/llvm/dist/llvm/lib/Target/RISCV/RISCVSubtarget.h, line 67
- external/bsd/llvm/dist/llvm/lib/Target/Sparc/SparcFrameLowering.cpp
- external/bsd/llvm/dist/llvm/lib/Target/Sparc/SparcISelLowering.cpp
- external/bsd/llvm/dist/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
- external/bsd/llvm/dist/llvm/lib/Target/SystemZ/SystemZLDCleanup.cpp
- external/bsd/llvm/dist/llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp
- external/bsd/llvm/dist/llvm/lib/Target/X86/X86CallFrameOptimization.cpp
- external/bsd/llvm/dist/llvm/lib/Target/X86/X86FastISel.cpp
- external/bsd/llvm/dist/llvm/lib/Target/X86/X86ISelLowering.cpp
- external/bsd/llvm/dist/llvm/lib/Target/X86/X86InstrInfo.cpp
- external/bsd/llvm/dist/llvm/lib/Target/X86/X86MachineFunctionInfo.cpp
- external/bsd/llvm/dist/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
- external/bsd/llvm/dist/llvm/lib/Target/XCore/XCoreISelLowering.cpp
- external/bsd/llvm/dist/llvm/lib/Transforms/IPO/PartialInlining.cpp
- external/bsd/llvm/dist/llvm/tools/llvm-exegesis/lib/RegisterAliasing.cpp
- external/bsd/llvm/dist/llvm/tools/llvm-exegesis/lib/RegisterAliasing.h
- external/bsd/llvm/dist/llvm/tools/llvm-exegesis/llvm-exegesis.cpp
- external/bsd/llvm/dist/llvm/unittests/tools/llvm-exegesis/X86/RegisterAliasingTest.cpp