#	$NetBSD: files.omap,v 1.7 2018/09/21 12:04:06 skrll Exp $
#
# Configuration info for Texas Instruments OMAP CPU support
# Based on xscale/files.pxa2x0
#

file	arch/arm/arm32/irq_dispatch.S

# Memory size in megabytes
defparam opt_omap.h				MEMSIZE

# Texas Instruments Peripheral Bus.
# addr: Address of the peripheral in the OMAP address space
# size: Number of bytes that the peripheral occupies in the OMAP address space
# intr: Interrupts connected to the first level interrupt controller should
#	give the first level interrupt controller's number.  Interrupts
#	connected to the second level interrupt controller should give the
#	second level interrupt controller's number plus 32 (the number of
#	interrupts that the first level controller has).
# mult: Used to multiply the offsets given within a driver.  For example, if
#	the driver expects byte registers at byte offsets, but they are mapped
#	in at word offsets, a mult of 4 would be specified.  Note that the
#	size parameter is not multiplied by mult.  If you specify a mult, in
#	general, you should probably be specifying a size to ensure that the
#	correct amount is mapped.
device tipb { [addr=-1], [size=0], [intr=-1], [mult=1] } : bus_space_generic
attach tipb at mainbus
file	arch/arm/omap/omap_tipb.c		tipb
defparam opt_omap.h				OMAP_TIPB_PBASE OMAP_TIPB_SIZE

# Extended Memory Interface Slow
# Same parameters as for TIPB, but with the addition of parameters to
# configure bus access.  A parameter is provided to to force halfword access
# instead of byte accesses:
#    nobyteacc: Allow 8-bit access for device with no lsb address line
# If this is set to 1, if an attempt is made to write a single byte to the
# bus, it will automatically get converted into reading a halfword, setting
# the byte that is being written into the appropriate byte of the halfword,
# and then writing the halfword to the bus.
#
# In addition to the nobyteacc parameter, a number of parameters are provided
# to configure bus timing via the EMIFS_CCS and EMIFS_ACS registers.  The cs
# parameter specifies which chip-select should have its configuration
# modified.
#
# NOTE: If the cs parameter is not specified, the EMIFS_CCS and EMIFS_ACS
# registers will not be modified and all of the bus timing parameters will be
# ignored.
#
# When cs is specified, EMIFS_CCS and EMIFS_ACS will be modified.  In addition
# to cs on your emifs device, you must specify the base parameter on the emifs
# bus to tell it where its registers are.  All fields of the EMIFS_CCS and
# EMIFS_ACS registers will be set.  The EMIFS will be set to be:
#
#	asynchronous, non-page mode (RDMODE = 0)
#	non-multiplexed protocol
#	16 bit wide
#	REF_CLK = TC_CK / 1
#
# The timing parameters are rdwst, oesetup, oehold, wrwst, welen, advhold,
# btwst and btmode.  All of them specify a number of nanoseconds, except
# btmode which is a simple 0/1 flag.
#
# For a read cycle, CS will be held low for rdwst nanoseconds.  The delay from
# driving CS low to driving OE low is specified by oesetup.  OE will go back
# high oehold nanoseconds before CS goes back high.
#
# For a write cycle, CS will be held low for wrwst (time before WE goes low) +
# welen (time WE is held low) + 1 REF_CLK cycle (time after WE goes high).
#
# For both read and write, advhold specifies how long ADV should be remain low
# after it is driven low at the same time as CS.
#
# The bus turn around time (amount of time that CS needs to be high between
# accesses) is specified by btwst and btmode.  See the TRM for more
# information.
#
# If btmode is not specified, it will be set to 0.  All other timing
# parameters will default to their minimum value.
#
device emifs { [addr=-1], [size=0], [intr=-1], [mult=1], [nobyteacc=0],
	       [cs=-1], [rdwst=0], [oesetup=0], [oehold=0],
	       [wrwst=0], [welen=0], [advhold=0], [btwst=0], [btmode=0]
	     } : bus_space_generic
attach emifs at mainbus
file	arch/arm/omap/omap_emifs.c		emifs
file	arch/arm/omap/omap_nobyteacc_space.c	emifs
file	arch/arm/omap/omap_nobyteacc_io.S	emifs
defparam opt_omap.h				OMAP_TC_CLOCK_FREQ

# OCP
device ocp { [addr=-1], [size=0], [intr=-1], [mult=1]} : bus_space_generic
attach ocp at mainbus
file	arch/arm/omap/omap_ocp.c		ocp

# TIPB/EMIFS/OCP common files
file	arch/arm/omap/omap_space.c		tipb | emifs | ocp
file	arch/arm/omap/omap_a2x_space.c		tipb | emifs | ocp
file	arch/arm/arm/bus_space_a2x.S		tipb | emifs | ocp
file	arch/arm/omap/omap_a4x_space.c		tipb | emifs | ocp
file	arch/arm/arm/bus_space_a4x.S		tipb | emifs | ocp

# NS16550 compatible serial ports
attach com at tipb with omapuart
file	arch/arm/omap/omap_com.c		omapuart

# INTC controller
define omapintc
file	arch/arm/omap/omap_intr.c		omapintc
# OMAP5912 specific INTC controller code
device omap5912intc: omapintc
attach omap5912intc at tipb
file	arch/arm/omap/omap5912_intr.c		omap5912intc

# MPU Timer
device omapmputmr
attach omapmputmr at tipb
file	arch/arm/omap/omap_mputmr.c		omapmputmr
defparam opt_omap.h				OMAP_MPU_TIMER_CLOCK_FREQ

# OMAP GPIO Block
device omapgpio
attach omapgpio at tipb
file  arch/arm/omap/omap_gpio.c       omapgpio	needs-count

# RTC
device omaprtc
attach omaprtc at tipb
file arch/arm/omap/omap_rtc.c			omaprtc