Defined in 2 files as a macro:
Defined in 2 files as a enumerator:
Referenced in 101 files:
- external/gpl3/binutils/dist/gas/bfin-lex.c, line 1299
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_except_sys_sstep.S, line 178
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_except_user_mode.S, line 220
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_disable.S, line 277
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_disable_enable.S, line 297
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_excpt.S, line 220
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_nested.S, line 215
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_nmi.S, line 247
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_pending.S, line 276
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_pending_2.S, line 211
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_timer.S, line 338
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_timer_reload.S, line 240
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_timer_tcount.S, line 196
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_timer_tscale.S, line 258
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_mmr_interr_ctl.s, line 331
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_mmr_loop.S, line 329
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_mmr_loop_user_except.S, line 227
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_mmr_ppop_illegal_adr.S, line 207
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_mmr_ppopm_illegal_adr.S, line 208
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_mmr_timer.S, line 213
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_mode_supervisor.S, line 216
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_mode_user.S, line 237
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_mode_user_superivsor.S, line 218
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_progctrl_clisti_interr.S, line 284
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_progctrl_csync_mmr.S, line 214
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_progctrl_excpt.S, line 192
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_progctrl_raise_rt_i_n.S, line 214
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ac_raise_mv.S, line 271
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ac_raise_mv_ppop.S, line 288
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ac_regmv_pushpop.S, line 288
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_dec_raise_pushpop.S, line 270
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex1_brcc_mv_pop.S, line 306
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex1_call_mv_pop.S, line 322
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex1_j_mv_pop.S, line 304
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex1_raise_brcc_mv_pop.S, line 306
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex1_raise_call_mv_pop.S, line 322
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex1_raise_j_mv_pop.S, line 304
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex2_brcc_mp_mv_pop.S, line 306
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex2_mmr_mvpop.S, line 315
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex2_mmrj_mvpop.S, line 315
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex2_raise_mmr_mvpop.S, line 314
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex2_raise_mmrj_mvpop.S, line 314
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex3_ls_brcc_mvp.S, line 330
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex3_ls_mmr_mvp.S, line 332
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex3_ls_mmrj_mvp.S, line 333
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex3_raise_ls_mmrj_mvp.S, line 332
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_wb_cs_lsmmrj_mvp.S, line 336
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_wb_raisecs_lsmmrj_mvp.S, line 336
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_wb_rti_lsmmrj_mvp.S, line 330
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_wb_rtn_lsmmrj_mvp.S, line 330
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_wb_rtx_lsmmrj_mvp.S, line 336
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/dbg_brprd_ntkn_src_kill.S, line 156
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/dbg_brtkn_nprd_src_kill.S, line 155
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/dbg_jmp_src_kill.S, line 154
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/dbg_tr_basic.S, line 236
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/dbg_tr_simplejp.S, line 231
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/dbg_tr_tbuf0.S, line 223
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/dbg_tr_umode.S, line 255
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_brtarget_stall.S, line 190
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_bug_ui.S, line 206
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_bug_ui2.S, line 206
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_bug_ui3.S, line 216
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_cc2stat_haz.S, line 228
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_cc_kill.S, line 217
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_cof.S, line 150
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_event_quad.S, line 166
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_excpt_dagprotviol.S, line 192
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_excpt_ifprotviol.S, line 191
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_excpt_ssstep.S, line 209
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_illegalcombination.S, line 538
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_kill_wbbr.S, 3 times
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_disable.S, line 150
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_kill.S, line 166
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_kill_01.S, line 166
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_kill_dcr.S, line 150
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_kill_dcr_01.S, line 150
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_lr.S, line 150
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lb_stall.S, line 166
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lc.S, line 150
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lc_stall.S, line 166
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lt_stall.S, line 166
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_nest_ppm.S, line 150
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_nest_ppm_1.S, line 150
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_nest_ppm_2.S, line 150
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_ppm.S, line 150
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_ppm_1.S, line 150
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_ppm_int.S, line 149
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_lsetup_kill.S, line 150
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_misaligned_fetch.S, line 211
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_more_ret_haz.S, line 209
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_mv2lp.S, line 150
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_oneins_zoff.S, line 166
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_popkill.S, line 192
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_rts_rti.S, line 165
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_ssstep_dagprotviol.S, line 198
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_stall_if2.S, line 187
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_undefinedinstruction1.S, line 1019
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_undefinedinstruction2.S, line 3051
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_undefinedinstruction3.S, line 5931
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_undefinedinstruction4.S, line 1215
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_usermode_protviol.S, 2 times