Defined in 6 files as a label:

• external/bsd/llvm/dist/llvm/test/MC/PowerPC/ppc-reloc.s, line 11 (as a label)
• external/bsd/llvm/dist/llvm/test/MC/PowerPC/ppc64-relocs-01.s, line 15 (as a label)
• external/gpl3/gdb/dist/gdb/testsuite/gdb.arch/amd64-entry-value.s, line 893 (as a label)
• external/gpl3/gdb/dist/gdb/testsuite/gdb.arch/amd64-invalid-stack-middle.S, line 174 (as a label)
• external/gpl3/gdb/dist/gdb/testsuite/gdb.dwarf2/dw2-common-block.S, line 233 (as a label)
• external/gpl3/gdb/dist/gdb/testsuite/gdb.dwarf2/typeddwarf-amd64.S, line 181 (as a label)

Defined in 116 files as a define:

• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_except_sys_sstep.S, line 117 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_except_user_mode.S, line 114 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_excpt.S, line 117 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_nested.S, line 116 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_nmi.S, line 116 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_pending_2.S, line 117 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_loopsetup_nested_prelc.s, line 32 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_loopsetup_nested_prelc.s, line 43 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_loopsetup_nested_prelc.s, line 72 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_loopsetup_nested_prelc.s, line 120 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_loopsetup_nested_prelc.s, line 161 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_loopsetup_prelc.s, line 32 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_loopsetup_prelc.s, line 66 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_loopsetup_prelc.s, line 121 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_loopsetup_topbotcntr.s, line 54 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_loopsetup_topbotcntr.s, line 85 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_mmr_interr_ctl.s, line 94 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_mmr_loop.S, line 113 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_mmr_loop_user_except.S, line 129 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_mmr_ppop_illegal_adr.S, line 115 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_mmr_ppopm_illegal_adr.S, line 115 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_mmr_timer.S, line 112 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_mode_supervisor.S, line 114 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_mode_user.S, line 117 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_mode_user_superivsor.S, line 114 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_progctrl_csync_mmr.S, line 117 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_progctrl_excpt.S, line 116 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_progctrl_raise_rt_i_n.S, line 114 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ac_raise_mv.S, line 116 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ac_raise_mv_ppop.S, line 116 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ac_regmv_pushpop.S, line 116 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_dec_raise_pushpop.S, line 116 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex1_brcc_mv_pop.S, line 116 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex1_call_mv_pop.S, line 116 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex1_j_mv_pop.S, line 116 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex1_raise_brcc_mv_pop.S, line 116 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex1_raise_call_mv_pop.S, line 116 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex1_raise_j_mv_pop.S, line 116 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex2_brcc_mp_mv_pop.S, line 116 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex2_mmr_mvpop.S, line 116 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex2_mmrj_mvpop.S, line 116 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex2_raise_mmr_mvpop.S, line 116 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex2_raise_mmrj_mvpop.S, line 116 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex3_ls_brcc_mvp.S, line 116 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex3_ls_mmr_mvp.S, line 116 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex3_ls_mmrj_mvp.S, line 116 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex3_raise_ls_mmrj_mvp.S, line 116 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_wb_cs_lsmmrj_mvp.S, line 116 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_wb_raisecs_lsmmrj_mvp.S, line 116 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_wb_rti_lsmmrj_mvp.S, line 116 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_wb_rtn_lsmmrj_mvp.S, line 116 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_wb_rtx_lsmmrj_mvp.S, line 116 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/hwloop-bits.S, line 59 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/hwloop-bits.S, line 76 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/hwloop-bits.S, line 91 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_bug_ui.S, line 117 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_bug_ui2.S, line 117 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_bug_ui3.S, line 117 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_cc2stat_haz.S, line 156 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_cc_kill.S, line 145 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_excpt_dagprotviol.S, line 113 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_excpt_ifprotviol.S, line 113 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_excpt_ssstep.S, line 121 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_illegalcombination.S, line 121 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_kill.S, line 398 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_kill.S, line 412 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_kill_01.S, line 400 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_kill_01.S, line 414 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lb_stall.S, line 464 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lb_stall.S, line 478 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lb_stall.S, line 493 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lb_stall.S, line 509 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lb_stall.S, line 526 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lb_stall.S, line 546 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lc.S, line 372 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lc.S, line 378 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lc.S, line 379 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lc.S, line 478 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lc.S, line 486 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lc.S, line 501 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lc.S, line 509 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lc.S, line 522 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lc.S, line 530 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lc.S, line 541 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lc.S, line 549 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lc.S, line 649 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lc.S, line 657 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lc.S, line 672 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lc.S, line 680 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lc.S, line 693 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lc.S, line 701 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lc.S, line 712 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lc.S, line 720 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lc_stall.S, line 468 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lc_stall.S, line 483 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lc_stall.S, line 499 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lc_stall.S, line 516 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lc_stall.S, line 534 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lc_stall.S, line 548 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lt_stall.S, line 464 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lt_stall.S, line 478 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lt_stall.S, line 493 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lt_stall.S, line 509 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lt_stall.S, line 526 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lt_stall.S, line 546 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_misaligned_fetch.S, line 125 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_more_ret_haz.S, line 123 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_popkill.S, line 394 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_popkill.S, line 442 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_regmv_usp_sysreg.S, line 69 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_ssstep_dagprotviol.S, line 117 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_undefinedinstruction1.S, line 120 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_undefinedinstruction2.S, line 120 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_undefinedinstruction3.S, line 121 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_undefinedinstruction4.S, line 120 (as a define)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_usermode_protviol.S, line 117 (as a define)

Referenced in 44 files:

• external/bsd/llvm/dist/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
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• external/bsd/llvm/dist/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp, line 691
• external/bsd/llvm/dist/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
  • line 999
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• external/bsd/llvm/dist/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp, line 160
• external/bsd/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp, line 51
• external/bsd/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h, line 108
• external/bsd/llvm/dist/llvm/test/MC/PowerPC/ppc64-relocs-01.s, line 11
• external/gpl3/gdb/dist/gdb/testsuite/gdb.arch/amd64-entry-value.s, line 128
• external/gpl3/gdb/dist/gdb/testsuite/gdb.arch/amd64-invalid-stack-middle.S, line 217
• external/gpl3/gdb/dist/gdb/testsuite/gdb.dwarf2/dw2-common-block.S
  • line 73
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• external/gpl3/gdb/dist/gdb/testsuite/gdb.dwarf2/typeddwarf-amd64.S
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• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_loopsetup_nested.s
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• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_loopsetup_nested_bot.s
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• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_loopsetup_nested_prelc.s
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• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_loopsetup_nested_top.s
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• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_loopsetup_overlap.s
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• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_loopsetup_preg_div2_lc1.s
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• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_loopsetup_preg_lc1.s
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• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_loopsetup_prelc.s
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• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/cec-multi-pending.S, line 29
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/fir.s, line 140
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/hwloop-bits.S, line 21
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/hwloop-nested.s
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• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/lp0.s, line 12
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/lsetup.s, line 96
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/push-pop.s, line 66
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/s1.s, line 20
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_kill.S
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• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_kill_01.S
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• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_kill_dcr.S
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• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_kill_dcr_01.S
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• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_lr.S
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• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_mv2lc.S
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• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_nest_ppm.S
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• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_nest_ppm_1.S
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• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_nest_ppm_2.S
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• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_ppm.S
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• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_ppm_1.S
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• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_ppm_int.S
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• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_lsetup_kill.S
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• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_mv2lp.S
  • line 387
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• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_oneins_zoff.S
  • line 421
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  • line 432
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• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_regmv_usp_sysreg.S, line 70
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/viterbi2.s, line 115