Defined in 2 files as a macro:
Defined in 3 files as a enumerator:
Referenced in 79 files:
- external/bsd/llvm/dist/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp, line 4252
- external/bsd/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h, line 110
- external/gpl3/binutils/dist/gas/bfin-lex.c, line 1729
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_disable.S
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_disable_enable.S
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_excpt.S, line 141
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_nested.S, line 137
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_nmi.S, line 137
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_pending.S
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_pending_2.S, line 140
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_timer.S
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_timer_reload.S
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_timer_tcount.S
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_timer_tscale.S
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_mmr_loop.S
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_mmr_loop_user_except.S
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_mmr_ppop_illegal_adr.S
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_mmr_ppopm_illegal_adr.S
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_mmr_timer.S
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_progctrl_clisti_interr.S
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_progctrl_csync_mmr.S
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ac_raise_mv.S, line 105
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ac_raise_mv_ppop.S, line 105
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ac_regmv_pushpop.S, line 105
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_dec_raise_pushpop.S, line 105
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex1_brcc_mv_pop.S, line 105
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex1_call_mv_pop.S, line 105
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex1_j_mv_pop.S, line 105
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex1_raise_brcc_mv_pop.S, line 105
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex1_raise_call_mv_pop.S, line 105
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex1_raise_j_mv_pop.S, line 105
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex2_brcc_mp_mv_pop.S, line 105
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex2_mmr_mvpop.S
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex2_mmrj_mvpop.S
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex2_raise_mmr_mvpop.S
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex2_raise_mmrj_mvpop.S
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex3_ls_brcc_mvp.S
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex3_ls_mmr_mvp.S
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex3_ls_mmrj_mvp.S
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex3_raise_ls_mmrj_mvp.S
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_wb_cs_lsmmrj_mvp.S
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_wb_raisecs_lsmmrj_mvp.S
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_wb_rti_lsmmrj_mvp.S
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_wb_rtn_lsmmrj_mvp.S
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_wb_rtx_lsmmrj_mvp.S
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/cec-no-snen-reti.S, line 24
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/cec-snen-reti.S, line 24
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/dbg_brprd_ntkn_src_kill.S, line 402
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/dbg_brtkn_nprd_src_kill.S, line 401
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/dbg_jmp_src_kill.S, line 400
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/lmu_cplb_multiple0.S
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/lmu_cplb_multiple1.S
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/lmu_excpt_align.S, line 26
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/lmu_excpt_default.S, line 29
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/lmu_excpt_illaddr.S, line 67
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/mmr-exception.s, line 14
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_brtarget_stall.S, line 147
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_bug_ui.S
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_bug_ui2.S
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_bug_ui3.S
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_cc2stat_haz.S
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_cc_kill.S
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_cof.S, line 346
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_excpt_dagprotviol.S
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_excpt_ifprotviol.S
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_illegalcombination.S
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_kill_wbbr.S
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_kill_dcr.S
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_loop_ppm_int.S
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_misaligned_fetch.S, line 113
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_more_ret_haz.S, line 111
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_popkill.S, line 149
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_ssstep_dagprotviol.S
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_stall_if2.S, line 144
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_undefinedinstruction1.S
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_undefinedinstruction2.S
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_undefinedinstruction3.S
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_undefinedinstruction4.S
- external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_usermode_protviol.S