Defined in 47 files as a macro:

• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_except_sys_sstep.S, line 21 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_except_user_mode.S, line 30 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_disable.S, line 35 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_disable_enable.S, line 35 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_excpt.S, line 31 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_nested.S, line 30 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_nmi.S, line 30 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_pending.S, line 35 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_pending_2.S, line 25 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_timer.S, line 35 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_timer_reload.S, line 35 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_timer_tcount.S, line 35 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_timer_tscale.S, line 35 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_mode_supervisor.S, line 30 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_mode_user.S, line 30 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_mode_user_superivsor.S, line 30 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_progctrl_clisti_interr.S, line 35 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_progctrl_csync_mmr.S, line 31 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_progctrl_excpt.S, line 30 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_progctrl_raise_rt_i_n.S, line 28 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ac_raise_mv.S, line 30 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ac_raise_mv_ppop.S, line 30 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ac_regmv_pushpop.S, line 30 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_dec_raise_pushpop.S, line 30 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex1_brcc_mv_pop.S, line 30 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex1_call_mv_pop.S, line 30 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex1_j_mv_pop.S, line 30 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex1_raise_brcc_mv_pop.S, line 30 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex1_raise_call_mv_pop.S, line 30 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex1_raise_j_mv_pop.S, line 30 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex2_brcc_mp_mv_pop.S, line 30 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex2_mmr_mvpop.S, line 30 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex2_mmrj_mvpop.S, line 30 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex2_raise_mmr_mvpop.S, line 30 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex2_raise_mmrj_mvpop.S, line 30 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex3_ls_brcc_mvp.S, line 30 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex3_ls_mmr_mvp.S, line 30 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex3_ls_mmrj_mvp.S, line 30 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex3_raise_ls_mmrj_mvp.S, line 30 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_wb_cs_lsmmrj_mvp.S, line 30 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_wb_raisecs_lsmmrj_mvp.S, line 30 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_wb_rti_lsmmrj_mvp.S, line 30 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_wb_rtn_lsmmrj_mvp.S, line 30 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_wb_rtx_lsmmrj_mvp.S, line 30 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_excpt_ssstep.S, line 27 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_misaligned_fetch.S, line 26 (as a macro)
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_more_ret_haz.S, line 26 (as a macro)

Referenced in 77 files:

• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_except_sys_sstep.S, line 20
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_except_user_mode.S
  • line 29
  • line 133
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_disable.S
  • line 34
  • line 120
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_disable_enable.S
  • line 34
  • line 121
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_excpt.S
  • line 30
  • line 139
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_nested.S
  • line 29
  • line 135
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_nmi.S
  • line 29
  • line 135
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_pending.S
  • line 34
  • line 119
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_pending_2.S
  • line 24
  • line 138
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_timer.S
  • line 34
  • line 119
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_timer_reload.S
  • line 34
  • line 120
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_timer_tcount.S
  • line 34
  • line 120
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_interr_timer_tscale.S
  • line 34
  • line 120
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_mmr_loop.S, line 134
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_mmr_loop_user_except.S, line 151
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_mmr_ppop_illegal_adr.S, line 136
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_mmr_ppopm_illegal_adr.S, line 136
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_mmr_timer.S, line 133
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_mode_supervisor.S
  • line 29
  • line 133
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_mode_user.S
  • line 29
  • line 136
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_mode_user_superivsor.S
  • line 29
  • line 133
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_progctrl_clisti_interr.S
  • line 34
  • line 119
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_progctrl_csync_mmr.S
  • line 30
  • line 136
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_progctrl_excpt.S
  • line 29
  • line 135
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_progctrl_raise_rt_i_n.S
  • line 27
  • line 133
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ac_raise_mv.S
  • line 29
  • line 135
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ac_raise_mv_ppop.S
  • line 29
  • line 135
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ac_regmv_pushpop.S
  • line 29
  • line 135
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_dec_raise_pushpop.S
  • line 29
  • line 135
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex1_brcc_mv_pop.S
  • line 29
  • line 135
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex1_call_mv_pop.S
  • line 29
  • line 135
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex1_j_mv_pop.S
  • line 29
  • line 135
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex1_raise_brcc_mv_pop.S
  • line 29
  • line 135
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex1_raise_call_mv_pop.S
  • line 29
  • line 135
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex1_raise_j_mv_pop.S
  • line 29
  • line 135
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex2_brcc_mp_mv_pop.S
  • line 29
  • line 135
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex2_mmr_mvpop.S
  • line 29
  • line 135
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex2_mmrj_mvpop.S
  • line 29
  • line 135
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex2_raise_mmr_mvpop.S
  • line 29
  • line 135
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex2_raise_mmrj_mvpop.S
  • line 29
  • line 135
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex3_ls_brcc_mvp.S
  • line 29
  • line 135
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex3_ls_mmr_mvp.S
  • line 29
  • line 135
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex3_ls_mmrj_mvp.S
  • line 29
  • line 135
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_ex3_raise_ls_mmrj_mvp.S
  • line 29
  • line 135
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_wb_cs_lsmmrj_mvp.S
  • line 29
  • line 135
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_wb_raisecs_lsmmrj_mvp.S
  • line 29
  • line 135
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_wb_rti_lsmmrj_mvp.S
  • line 29
  • line 135
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_wb_rtn_lsmmrj_mvp.S
  • line 29
  • line 135
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/c_seq_wb_rtx_lsmmrj_mvp.S
  • line 29
  • line 135
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/cec-multi-pending.S, line 43
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/dbg_tr_basic.S, line 87
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/dbg_tr_simplejp.S, line 88
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/dbg_tr_tbuf0.S, line 86
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/dbg_tr_umode.S, line 90
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/lmu_cplb_multiple0.S, line 95
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/lmu_cplb_multiple1.S, line 95
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/lmu_excpt_default.S, line 26
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/lmu_excpt_illaddr.S, line 50
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/lmu_excpt_prot0.S, line 114
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/lmu_excpt_prot1.S, line 116
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_bug_ui.S, line 138
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_bug_ui2.S, line 138
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_bug_ui3.S, line 138
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_cc2stat_haz.S, line 176
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_cc_kill.S, line 165
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_excpt_dagprotviol.S, line 140
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_excpt_ifprotviol.S, line 140
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_excpt_ssstep.S
  • line 26
  • line 147
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_illegalcombination.S, line 142
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_misaligned_fetch.S
  • line 25
  • line 144
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_more_ret_haz.S
  • line 25
  • line 142
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_ssstep_dagprotviol.S, line 141
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_undefinedinstruction1.S, line 141
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_undefinedinstruction2.S, line 142
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_undefinedinstruction3.S, line 142
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_undefinedinstruction4.S, line 141
• external/gpl3/gdb/dist/sim/testsuite/sim/bfin/se_usermode_protviol.S, line 144