/* $NetBSD: rgmiireg.h,v 1.1 2010/03/18 13:47:04 kiyohara Exp $ */ /* * Copyright (c) 2010 KIYOHARA Takashi * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef _IBM4XX_RGMIIREG_H_ #define _IBM4XX_RGMIIREG_H_ /* RGMII (reduced GMII) Bridge (405EX/440GX(EMAC 2, 3)) */ #define RGMII0_SIZE 0x8 #define RGMII0_FER 0x0 /* Function Enable Register */ #define FER_MDIOEN_MASK 0x000c0000 /* MDIO enable */ #define FER_MDIOEN(emac) (1 << ((1 - ((emac) % 2)) + 18)) #define FER_CHCFG_MASK 0x7 /* EMAC n Mask */ #define FER_CHCFG_RTBI 0x4 /* RTBI enabled */ #define FER_CHCFG_RGMII 0x5 /* RGMII enabled */ #define FER_CHCFG_TBI 0x6 /* TBI enabled */ #define FER_CHCFG_GMII 0x7 /* GMII enabled */ #define FER_CHCFG(rgmii, val) ((val) << ((rgmii) << 2)) #define RGMII0_SSR 0x4 /* Speed Select Register */ #define SSR_SP_MASK 0x7 #define SSR_SP_10MBPS 0x0 #define SSR_SP_100MBPS 0x2 #define SSR_SP_1000MBPS 0x4 #define SSR_SP(emac, sp) ((sp) << (((emac) % 2) << 3)) #endif /* _IBM4XX_RGMIIREG_H_ */ |