OperandType identifier - Netbsd-lockdoc source code (lockdoc-9.3-vfs-0.1) - Bootlin

Training courses

Kernel and Embedded Linux

Bootlin training courses

Embedded Linux, kernel,

Yocto Project, Buildroot, real-time,

graphics, boot time, debugging...

Elixir Cross Referencer

Defined in 4 files as a member:

Defined in 5 files as a enum:

Referenced in 40 files:

external/bsd/llvm/dist/clang/include/clang/Sema/DelayedDiagnostic.h
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external/bsd/llvm/dist/llvm/include/llvm/DebugInfo/DWARF/DWARFDebugFrame.h, line 118
external/bsd/llvm/dist/llvm/include/llvm/MC/MCInstrDesc.h
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external/bsd/llvm/dist/llvm/lib/AsmParser/LLParser.cpp
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external/bsd/llvm/dist/llvm/lib/AsmParser/LLParser.h, line 567
external/bsd/llvm/dist/llvm/lib/DebugInfo/DWARF/DWARFDebugFrame.cpp
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external/bsd/llvm/dist/llvm/lib/MC/MCInstrAnalysis.cpp, line 30
external/bsd/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp, line 148
external/bsd/llvm/dist/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
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external/bsd/llvm/dist/llvm/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp, line 523
external/bsd/llvm/dist/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp, line 231
external/bsd/llvm/dist/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp, line 143
external/bsd/llvm/dist/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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external/bsd/llvm/dist/llvm/lib/Target/AMDGPU/SIInstrInfo.h
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external/bsd/llvm/dist/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
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external/bsd/llvm/dist/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h, line 386
external/bsd/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
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external/bsd/llvm/dist/llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp, line 101
external/bsd/llvm/dist/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
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external/bsd/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp, line 137
external/bsd/llvm/dist/llvm/lib/Target/WebAssembly/InstPrinter/WebAssemblyInstPrinter.cpp
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external/bsd/llvm/dist/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCCodeEmitter.cpp
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external/bsd/llvm/dist/llvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp, line 170
external/bsd/llvm/dist/llvm/lib/Target/WebAssembly/WebAssemblySetP2AlignOperands.cpp, line 66
external/bsd/llvm/dist/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
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external/bsd/llvm/dist/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
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external/bsd/llvm/dist/llvm/tools/llvm-exegesis/lib/Latency.cpp
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external/bsd/llvm/dist/llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp
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external/bsd/llvm/dist/llvm/tools/llvm-exegesis/lib/Uops.cpp
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external/bsd/llvm/dist/llvm/utils/TableGen/AsmWriterEmitter.cpp
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external/bsd/llvm/dist/llvm/utils/TableGen/AsmWriterInst.cpp
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external/bsd/llvm/dist/llvm/utils/TableGen/AsmWriterInst.h
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external/bsd/llvm/dist/llvm/utils/TableGen/CodeGenInstruction.cpp
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external/bsd/llvm/dist/llvm/utils/TableGen/CodeGenInstruction.h, line 111
external/bsd/llvm/dist/llvm/utils/TableGen/GlobalISelEmitter.cpp, line 1613
external/bsd/llvm/dist/llvm/utils/TableGen/InstrInfoEmitter.cpp
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external/bsd/llvm/dist/llvm/utils/TableGen/WebAssemblyDisassemblerEmitter.cpp, line 86
external/bsd/llvm/dist/llvm/utils/TableGen/X86DisassemblerTables.cpp
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external/bsd/llvm/dist/llvm/utils/TableGen/X86RecognizableInstr.cpp
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external/bsd/llvm/dist/llvm/utils/TableGen/X86RecognizableInstr.h, line 241