RegClass identifier - Netbsd-lockdoc source code (lockdoc-9.3-vfs-0.2) - Bootlin

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Kernel and Embedded Linux

Bootlin training courses

Embedded Linux, kernel,

Yocto Project, Buildroot, real-time,

graphics, boot time, debugging...

Elixir Cross Referencer

Defined in 3 files as a member:

Referenced in 45 files:

external/bsd/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/Utils.h, line 48
external/bsd/llvm/dist/llvm/include/llvm/CodeGen/MachineRegisterInfo.h, line 717
external/bsd/llvm/dist/llvm/include/llvm/CodeGen/RegisterClassInfo.h, line 75
external/bsd/llvm/dist/llvm/include/llvm/CodeGen/RegisterScavenging.h
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external/bsd/llvm/dist/llvm/lib/CodeGen/GlobalISel/Utils.cpp
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external/bsd/llvm/dist/llvm/lib/CodeGen/LiveIntervals.cpp
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external/bsd/llvm/dist/llvm/lib/CodeGen/MachineRegisterInfo.cpp
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external/bsd/llvm/dist/llvm/lib/CodeGen/RegisterClassInfo.cpp
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external/bsd/llvm/dist/llvm/lib/CodeGen/RenameIndependentSubregs.cpp
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external/bsd/llvm/dist/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
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external/bsd/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
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external/bsd/llvm/dist/llvm/lib/CodeGen/TargetInstrInfo.cpp
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external/bsd/llvm/dist/llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp, line 520
external/bsd/llvm/dist/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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external/bsd/llvm/dist/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
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external/bsd/llvm/dist/llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp
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external/bsd/llvm/dist/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp, line 4902
external/bsd/llvm/dist/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
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external/bsd/llvm/dist/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
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external/bsd/llvm/dist/llvm/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp, line 567
external/bsd/llvm/dist/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
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external/bsd/llvm/dist/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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external/bsd/llvm/dist/llvm/lib/Target/AMDGPU/SIInstrInfo.h
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external/bsd/llvm/dist/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
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external/bsd/llvm/dist/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp, line 825
external/bsd/llvm/dist/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
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external/bsd/llvm/dist/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
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external/bsd/llvm/dist/llvm/lib/Target/ARM/ARMISelLowering.cpp
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external/bsd/llvm/dist/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
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external/bsd/llvm/dist/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp, line 9093
external/bsd/llvm/dist/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp, line 562
external/bsd/llvm/dist/llvm/lib/Target/AVR/InstPrinter/AVRInstPrinter.cpp
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external/bsd/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp, line 458
external/bsd/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp, line 824
external/bsd/llvm/dist/llvm/lib/Target/Hexagon/RDFRegisters.cpp
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external/bsd/llvm/dist/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp, line 3580
external/bsd/llvm/dist/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
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external/bsd/llvm/dist/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
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external/bsd/llvm/dist/llvm/lib/Target/X86/X86FrameLowering.cpp
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external/bsd/llvm/dist/llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp
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external/bsd/llvm/dist/llvm/tools/llvm-exegesis/lib/RegisterAliasing.cpp
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external/bsd/llvm/dist/llvm/tools/llvm-exegesis/lib/RegisterAliasing.h, line 45
external/bsd/llvm/dist/llvm/utils/TableGen/CodeGenDAGPatterns.cpp
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external/bsd/llvm/dist/llvm/utils/TableGen/CodeGenRegisters.cpp
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external/bsd/llvm/dist/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
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