Defined in 1 files as a prototype:

• external/bsd/llvm/dist/llvm/include/llvm/CodeGen/MachineInstr.h, line 1247 (as a prototype)

Defined in 2 files as a function:

• external/bsd/llvm/dist/llvm/include/llvm/MC/MCInstrDesc.h, line 412 (as a function)
• external/bsd/llvm/dist/llvm/lib/CodeGen/MachineInstr.cpp, line 1179 (as a function)

Referenced in 32 files:

• external/bsd/llvm/dist/llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp, line 82
• external/bsd/llvm/dist/llvm/lib/CodeGen/ImplicitNullChecks.cpp, line 231
• external/bsd/llvm/dist/llvm/lib/CodeGen/LiveRangeShrink.cpp, line 159
• external/bsd/llvm/dist/llvm/lib/CodeGen/MachineCSE.cpp, line 365
• external/bsd/llvm/dist/llvm/lib/CodeGen/MachineInstr.cpp
  • line 997
  • line 1107
  • line 1192
• external/bsd/llvm/dist/llvm/lib/CodeGen/MachineLICM.cpp, line 917
• external/bsd/llvm/dist/llvm/lib/CodeGen/MachinePipeliner.cpp
  • line 1040
  • line 3543
  • line 3543
• external/bsd/llvm/dist/llvm/lib/CodeGen/PeepholeOptimizer.cpp
  • line 1694
  • line 1829
• external/bsd/llvm/dist/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp, line 506
• external/bsd/llvm/dist/llvm/lib/CodeGen/TargetInstrInfo.cpp, line 912
• external/bsd/llvm/dist/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
  • line 892
  • line 949
  • line 1123
• external/bsd/llvm/dist/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
  • line 1088
  • line 1088
• external/bsd/llvm/dist/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  • line 2149
  • line 2149
• external/bsd/llvm/dist/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp, line 364
• external/bsd/llvm/dist/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp, line 144
• external/bsd/llvm/dist/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp, line 2068
• external/bsd/llvm/dist/llvm/lib/Target/ARM/ARMOptimizeBarriersPass.cpp, line 46
• external/bsd/llvm/dist/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
  • line 1316
  • line 2124
• external/bsd/llvm/dist/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp, line 254
• external/bsd/llvm/dist/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp, line 690
• external/bsd/llvm/dist/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
  • line 725
  • line 827
  • line 837
• external/bsd/llvm/dist/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
  • line 1817
  • line 1817
• external/bsd/llvm/dist/llvm/lib/Target/Hexagon/HexagonStoreWidening.cpp, line 271
• external/bsd/llvm/dist/llvm/lib/Target/Hexagon/RDFDeadCode.cpp, line 61
• external/bsd/llvm/dist/llvm/lib/Target/Lanai/LanaiDelaySlotFiller.cpp, line 165
• external/bsd/llvm/dist/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
  • line 94
  • line 94
• external/bsd/llvm/dist/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp, line 927
• external/bsd/llvm/dist/llvm/lib/Target/PowerPC/PPCQPXLoadSplat.cpp, line 76
• external/bsd/llvm/dist/llvm/lib/Target/Sparc/DelaySlotFiller.cpp, line 214
• external/bsd/llvm/dist/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp, line 215
• external/bsd/llvm/dist/llvm/tools/llvm-mca/InstrBuilder.cpp, line 374
• external/bsd/llvm/dist/llvm/tools/llvm-mca/InstructionInfoView.cpp, line 76