1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 | // SPDX-License-Identifier: GPL-2.0+ OR MIT // // Device Tree Source for UniPhier PXs3 Reference Board // // Copyright (C) 2017 Socionext Inc. // Author: Masahiro Yamada <yamada.masahiro@socionext.com> /dts-v1/; #include "uniphier-pxs3.dtsi" #include "uniphier-support-card.dtsi" / { model = "UniPhier PXs3 Reference Board"; compatible = "socionext,uniphier-pxs3-ref", "socionext,uniphier-pxs3"; chosen { stdout-path = "serial0:115200n8"; }; aliases { serial0 = &serial0; serial1 = &serial1; serial2 = &serial2; serial3 = &serial3; i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; i2c3 = &i2c3; i2c6 = &i2c6; }; memory@80000000 { device_type = "memory"; reg = <0 0x80000000 0 0xa0000000>; }; }; ðsc { interrupts = <4 8>; }; &serial0 { status = "okay"; }; &serial2 { status = "okay"; }; &serial3 { status = "okay"; }; &gpio { xirq4 { gpio-hog; gpios = <UNIPHIER_GPIO_IRQ(4) 0>; input; }; }; &i2c0 { status = "okay"; }; &i2c1 { status = "okay"; }; &i2c2 { status = "okay"; }; &i2c3 { status = "okay"; }; &sd { status = "okay"; }; ð0 { status = "okay"; phy-handle = <ðphy0>; }; &mdio0 { ethphy0: ethphy@0 { reg = <0>; }; }; ð1 { status = "okay"; phy-handle = <ðphy1>; }; &mdio1 { ethphy1: ethphy@0 { reg = <0>; }; }; &usb0 { status = "okay"; }; &usb1 { status = "okay"; }; &pcie { status = "okay"; }; &nand { status = "okay"; }; |